1. Field of the Invention
The present invention concerns a method of manufacturing a semiconductor device such as an integrated circuit, and also the pattern of alignment marks prepared for precise positioning of masks, or for testing the precision of alignment among plural layers for a semiconductor device.
2. Description of the Prior Art
For the purpose of ascertaining that a predetermined pattern of each layer of a multi-layer semiconductor device is correctly formed at a predetermined position on a semiconductor substrate, it is conventional to cause an alignment mark of a second mask for making a pattern of a second layer to be surrounded by, or to surround, an alignment mark printed at a predetermined position of the substrate by moving the second mask relative to the substrate. Shapes of such marks are shown in FIGS. 1A and 1B, and these marks are usually printed along one edge of a chip where elements of the device are not fabricated.
Referring to FIG. 1A, the second art practice is to position correctly a second mask for the second layer by moving it such that a mark 2 is surrounded by a printed mark 1 made on the surface of a substrate by a first mask for the first layer. In FIG. 1A, 1a denotes an edge or step formed on the substrate when mark 1 is made by a conventional patterning process for the first layer, for example, a selective etching process which has been carried out by using the first mask, and 2a denotes a pattern or contour of the second mark 2.
Similarly, a second mask for the second layer of FIG. 1B is correctly positioned or registered by placing a mark 11 made on the second mask for the second layer into a mark 12 formed on the substrate by the first mask. Also in FIG. 1B, 12a denotes an edge or step formed to the substrate, and 11a a pattern or contour of the mark 11.
In FIG. 1A, the distance L, the length of the mark 2, is in the order of 18 to 20 .mu.m, and the distance W, the width of mark 2, is approximately 6 .mu.m. The distance between the patterns 1a and 2a is in order of 2 .mu.m. Whether or not the mark 2 correctly is surrounded by the mark 1 formed on the substrate is ascertained by visually examining the uniformity or symmetry of the distance or gap between the patterns 1a and 2a with a microscope. In FIG. 1B, the length of the pattern 12a is approximately 14 .mu.m, and that of pattern 11a in the order of 10 .mu.m. The distance between the patterns 11a and 12a, in the order of 2 .mu.m, is also examined in the manner described above.
The patterns of the marks shown in FIGS. 1A and 1B not only make it possible to superimpose correctly the second mask for the second layer relative to the predetermined pattern of the elements of an integrated circuit and the like already formed on the substrate, but also enable testing or determination if each pattern is correctly positioned after the patterns of all layer have been formed on the substrate.
Where the predetermined patterns are used to form only two layers of a semiconductor device, difficult problems are not likely to be encountered with the marks shown in FIGS. 1A and 1B. However, where multi-layer patterns are to be formed on predetermined positions of the substrate, for example, where three or more patterns are to be formed, the method described above by reference to the patterns of FIG. 1A and FIG. 1B has been found ineffective.
Referring to FIG. 2A, for example, alignment of each layer will be realized by a method wherein an alignment mark 22 of the second layer is placed in a printed alignment mark formed on the substrate by a mark 21 of the first mask. Then, an alignment mark 23 of a third mask is placed on a printed alignment mark on the substrate made by using the mark 22 of the second mask. In the drawing, the marks printed on the substrate coincide with the alignment marks of the first and second masks.
In aligning these patterns, it is possible to ascertain the relative positioning of the mark printed by mark 21 of the first mask and the mark 22 of the second mask, and also that of the mark on the substrate printed by mark 22 of the second layer and the mark 23 of the third mask. However, it is difficult to ascertain the relative positioning of the mark on the substrate printed by mark 21 of the first mask and the mark 23 of the third mask because the symmetry of the gap between these marks can hardly be ascertained visually due to the interposing mark 22.
This means that alignment of the pattern of the third mask could be inaccurate and also that relative positioning of the pattern of each mask cannot be ascertained.
FIG. 2B illustrates another prior art usage where three masks, namely the first, second and third masks, are used. By using a mark 21 of the first mask, two alignment marks each of which is identical to mark 21 are printed on the substrate. An alignment mark 22 of the second mask is placed at a position in one of the printed marks 21 by movement of the second mask. When the process following formation of the mark corresponding to mark 22 is over, alignment mark 23 of the third mask is placed at a position in the other alignment mark 21 printed on the substrate by movement of the third mask. In the alignment illustrated, marks 22 and 23, shown by solid lines, are correctly positioned relative to the mark printed on the substrate corresponding to mark 21 of the first mask. However, there is no way to visually ascertain if marks printed on the substrate corresponding to marks 22 and 23 of the second and third masks are correctly positioned relative to each other. For example, if the mark corresponding to mark 22 of the second mask is printed on the substrate at a position shown by the dotted line with a positioning error within tolerance limits between the first and second patterns, it is difficult to visually ascertain whether the mark 23 is within the tolerance range with respect to the second pattern represented by the mark 22.